Power management in a data acquisition system

ABSTRACT

A data acquisition system includes a programmable gain amplifier, an analog-to-digital converter, a filter, and control circuitry. The programmable gain amplifier is operatively connected to receive an analog input signal on its input and generates an amplified signal on its output in accordance with gain control signals. The analog-to-digital converter is operatively connected to receive the amplified signal from the amplifier and generates a digitized signal on its output. The filter is operatively connected to receive the digitized signal from the converter and generates a filtered digital signal on its output. The control circuitry is operatively connected to the amplifier and to the converter and is also responsive to the gain control signals for dynamically adjusting power between the amplifier and converter when the gain control signals are changed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to electronic processing arrangements ina data acquisition system. More particularly, it relates to a method forreducing overall power in a data acquisition system. The presentinvention has use especially, but not exclusively, in the field ofseismic sensing applications where it is desired to achieve significantpower savings.

2. Description of the Prior Art

As is generally known in the art, a typical data acquisition system 100comprises a PGA (programmable gain amplifier) block 102, an ADC(analog-to-digital converter) block 104, and a decimation filter block106, as shown in FIG. 1 and labeled as “Prior Art.” The system 100 maybe used for converting an analog input signal of a signal source(seismic sensor or transducer) to a digital output signal. Specifically,the analog input signal is applied through input terminals 108, 110 tothe PGA block 102 which, in turn, produces an amplified signal on itsoutput lines 112, 114. The output lines 112, 114 from the PGA block 102are coupled to the input of the ADC block 104 which generates adigitized signal on its output lines 116, 118. The digitized signal ispassed to the decimation filter block 106 which produces the filtereddigital output signal on output terminals 120, 122. The gain of the PGAblock 102 is controlled by gain control signals at gain control lines124-128. Since the input terminals 108, 110 may receive different inputsignals each having different voltage characteristics, the amount ofamplification required to be provided by the amplifier block 102 can beadjusted via the signals applied at gain control lines 124-128 dependingupon the signal level applied to the input terminals 108, 110.

In seismic applications, the dynamic range, power consumption andlinearity of the PGA block 102 are critical parameters. Further, powerconservation is a high priority since any power savings achieved willresult in significant reduced cost for systems used for conductingseismic exploration. The total noise power of a channel in the digitalacquisition system 100 is given by the sum (in RMS sense) of the noisepower of the amplifier block 102 and the noise power of the ADC block104. Depending upon the gain setting of PGA, the use of the PGA block102 will reduce the ADC block's noise when that noise is input-referredto the PGA block's input. As defined herein, the “input-referred” noiseat the input of the PGA block 102 means the noise of the ADC block 104divided by the gain of the PGA block. The PGA block 102 is typicallydesigned and rated for its input-referred noise. As the gain of theamplifier block 102 is increased, the noise at its output on lines 112,114 will also be increased. Accordingly, at a lower gain setting of thePGA block 102, the contribution of the noise power from the amplifierwill be invariably small when compared to the noise power from the ADCblock 104, as the ADC block 104 may have a relatively high noise power.

However, the use of the PGA block 102 in the data acquisition system 100of FIG. 1 suffers from a drawback of being power inefficient since thereis no control of the power in either the amplifier block 102 and/or theADC block 104 when the gain settings in the PGA block 102 are changed.It would therefore be desirable to provide a technique that reduces theoverall power in a data acquisition system when the gain settings of thePGA block 102 are modified.

SUMMARY OF THE INVENTION

Accordingly, it is a general object of the present invention to providea novel method for reducing overall power in a data acquisition system,which has been traditionally unavailable.

It is an object of the present invention to provide a method forreducing overall power in a data acquisition system when the gainsettings in a PGA block are changed, but still maintaining substantiallythe same performance.

It is another object of the present invention to provide a method forreducing overall power in a data acquisition system in which power isdynamically shifted between a PGA block and an ADC block dependent uponchanges in gain settings.

It is still another object of the present invention to provide a methodof modifying the PGA and ADC circuitry when the power in the PGA and ADCblocks are modified, but the overall performance is maintained to besubstantially the same.

It is still another object of the present invention to provide a dataacquisition system which includes first current control circuitryconnected to a programmable gain amplifier and being responsive to gaincontrol signals for controlling the current level in the amplifier andsecond current control circuitry connected to an analog-to-digitalconverter and being also responsive to the gain control signals forcontrolling the current level in the converter.

In a preferred embodiment of the present invention, there is provided adata acquisition system which includes a programmable gain amplifier, ananalog-to-digital converter, a filter, and control circuitry. Theprogrammable gain amplifier is operatively connected to receive ananalog input signal on its input and generates an amplified signal onits output in accordance with gain control signals. Theanalog-to-digital converter is operatively connected to receive theamplified signal from the amplifier and generates a digitized signal onits output. The filter is operatively connected to receive the digitizedsignal from the converter and generates a filtered digital signal on itsoutput. The control circuitry is operatively connected to the amplifierand to the converter and is also responsive to the gain control signalsfor dynamically adjusting power between the amplifier and the converterwhen the gain control signals are changed.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and advantages of the present invention willbecome more fully apparent from the following detailed description whenread in conjunction with the accompanying drawings with like referencenumerals indicating corresponding parts throughout, wherein:

FIG. 1 is a block diagram of a conventional data acquisition system,which has been labeled “Prior Art”;

FIG. 2 is a more detailed block diagram of the PGA block 102 of FIG. 1,illustrating an exemplary gain control circuitry and labeled “PriorArt”;

FIG. 3 is a block diagram of a data acquisition system, constructed inaccordance with principles of the present invention;

FIG. 4 is a representation of one circuit design of one of theamplifiers 130, 132 for implementing the PGA block 202 of FIG. 3;

FIG. 5 is a schematic circuit diagram for implementing a portion of onestage of the multi-stage amplifier 400 of FIG. 4; and

FIG. 6 is a schematic circuit diagram for implementing the front endportion of a switched capacitor delta-sigma modulator of the ADC 204 inFIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

It is to be distinctly understood at the outset that the presentinvention shown in the drawings and described in detail in conjunctionwith the preferred embodiments is not intended to serve as a limitationupon the scope or teachings thereof, but is to be considered merely asan exemplification of the principles of the present invention.

Before describing in detail the present invention, it is believed thatit would be helpful as a background to explain the effect of theamplifier gain on the total output noise and input-referred noise asshown in Table I below for the PGA block 102 and the ADC block 104 inthe conventional data acquisition system of FIGS. 1 and 2. TABLE I InputAmplifier ADC Noise, Total Output Referred Gain, Noise, v_(namp),v_(nadc), Noise, v_(nout), Noise, v_(nin), A (nV/√Hz) (nV/√Hz) (nV/√Hz)(nV/√Hz) 1 6 60 60.29925373 60.29925373 2 6 60 61.18823416 30.59411708 46 60 64.62197769 16.15549442 8 6 60 76.83749085 9.604686356 16 6 60113.2077736 7.075485849 32 6 60 201.1566554 6.28614548 64 6 60388.6592338 6.072800528 128 6 60 770.3401846 6.01828692

The total output noise v_(nout) is determined mathematically fromequation (1) below:v _(nout)=√{square root over ([(A·v _(namp))²+(v _(nadc))²])}  (1)

Where

-   -   A is the gain of the PGA    -   v_(namp) is the noise of the PGA    -   v_(nadc) is the noise of the ADC

Similarly, the input-referred noise Vnin is given by equation (2) below:v _(nin)=√{square root over ([(v _(namp))²+(v _(nadc) /A)²])}  (2)

It should be apparently clear from Table I above that the contributionof the amplifier noise to the total noise (amplifier noise and ADCnoise) becomes a significant portion only beyond a certain gain of theamplifier (e.g., gain of 16). In other words, at lower gain settings(e.g., 1, 2, 4, 8) the total output noise, v_(nout), and theinput-referred noise, v_(nin), are dominated by the ADC noise and at thehigher gain settings (e.g., gain of 32, 64, 128) the total output noiseand the input-referred noise are dominated by the PGA noise.

Therefore, the noise of the amplifier can be made to be higher at alower gain setting without degrading the overall performance of thesystem. The inventors of the present invention have realized that thenoise of the amplifier at the lower gain settings can be increased tohigher acceptable levels, which will also lead to significant savings inpower.

In Table II below, the effect of amplifier gain (with its noise beingvaried) on the total output noise and the input-referred noise for adata acquisition system in accordance with the present invention isillustrated. TABLE II Input Amplifier ADC Noise, Total Output ReferredGain, Noise, v_(namp), v_(nadc), Noise, v_(nout), Noise, v_(nin), A(nV/√Hz) (nV/√Hz) (nV/√Hz) (nV/√Hz) 1 24 60 64.62197769 60.29925373 2 1860 69.79142274 30.59411708 4 12 60 76.83749085 16.15549442 8 6 6076.83749085 9.604686356 16 6 80 124.9639948 7.075485849 32 6 90212.0471646 6.28614548 64 6 100 396.807258 6.072800528 128 6 120777.3184676 6.01828692

As can be seen from Table II above, the noise of the amplifier has beenincreased for the lower gain settings (gain of 1 or 2) and this stilldoes not contribute significantly to the total output noise. In view ofthis, the amplifier noise can be increased at the lower gain settings byreducing the current and thus saving power, but will not degrade theoverall system's performance.

In addition, the inventors have recognized that the noise performance ofthe ADC block can be degraded (e.g., noise made higher) for theamplifier block operated at higher gain settings, thereby reducing powerconsumption in the ADC block so as to achieve further power savings.This savings in power is achieved without sacrificing the overallsignal-to-noise performance.

FIG. 2 is a more detailed block diagram of the prior art PGA block 102of FIG. 1 which includes gain control circuitry. The PGA block 102consists of first and second operational amplifiers 130, 132 andresistors R1 a-R3 a and R1 b-R3 b. The positive input voltage +Vin isapplied on the line 108 connected to the non-inverting input of theoperational amplifier 130, and the negative input voltage −Vin isapplied to the non-inverting input of the operational amplifier 132. Byselectively closing one pair of switches S1 a, S1 b; S2 a, S2 b; or S3a, S3 b, the gain of the PGA block 102 may be programmably set. A gaincontrol decoder 134 receives gain control signals gc1-gc3 on therespective gain control lines 124-128 and generates a plurality ofswitch control signals sc1, sc2 . . . scn for selectively configuring(activating and deactivating) of the corresponding switches Sla-Slbthrough S3 a-S3 b to achieve the desired gain.

Referring now to FIG. 3, there is illustrated in block diagram form adata acquisition system 200, which is constructed in accordance with theprinciples of the present invention. The system 200 comprises a PGA(programmable gain amplifier) block 202, an ADC (analog-to-digitalconverter) block 204, and a decimation filter block 206. The system 200may be used for converting an analog input signal of a signal source(seismic sensor or transducer) to a digital output signal. Specifically,the analog input signal is applied through input terminals 208, 210 tothe PGA block 202 which, in turn, produces an amplified signal on itsoutput lines 212, 214. The output lines 212, 214 from the PGA block 202are coupled to the input of the ADC block 204 which generates adigitized signal on its output lines 216, 218. The digitized signal ispassed to the decimation filter block 206, which produces the digitaloutput signal on output terminals 220, 222. The gain of the PGA block202 using the gain control circuitry of FIG. 2 is controlled by gaincontrol lines 224-228. As thus far described, the system 200 isidentical in its construction as the data acquisition system 100 of FIG.1.

Unlike the conventional data acquisition system of FIG. 1, the gaincontrol lines 224-228 are not only connected to the PGA block 202 so ascontrol the closed loop setting of the operational amplifiers 130, 132via the switch control signals SC1, SC2 . . . SCn, but the same controllines are also used to vary the current levels in the operationalamplifiers 130, 132 dependent upon the gain setting. While the currentlevels may be changed for each gain change listed in Table II, thecurrent levels can be alternatively varied only when there is a changein gain ranges. For example, the gain settings from 1 to 4 may bedefined as a “low gain” range; the gain settings from 8 to 16 may bedefined as a “mid-gain” range; and the gain settings from 32 to 128 maybe defined as a “high gain” range. Therefore, the current level can bevaried only when there is a change between the low gain and mid-gainranges or between the mid-gain and high gain ranges.

It should be clearly understood that in an amplifier the thermal noiseis essentially due to the input stage and is further due to the inputtransistors in a properly designed amplifier. This thermal noise poweris inversely proportional to the transconductance, gm, of the inputtransistors. This transconductance is, in turn, directly proportional tothe square root of the size of the transistors and the current flowingtherethrough. Accordingly, by decreasing the current and/or size of thetransistors, thermal noise level will be increased so as to achieve asavings in power.

However, there are some adverse implications encountered when thecurrent is decreased, such as the proper mode and/or region of operationof the transistors as well as the bandwidth of the amplifier beingdegraded. Consequently, it may be required to simultaneously re-size theinput transistors as the current is being modified. Further, since thebandwidth of the amplifier is dependent upon the transconductance of thepair of input transistors and loading capacitors, it may be alsonecessary to modify the capacitors when the current is being varied.

In FIG. 4, there is depicted one circuit design for implementing the PGAblock 202 of FIG. 3 which consists of a multi-stage amplifier 400 formedof a plurality (three shown in the exemplary amplifier) of stages 402,404 and 406 each having its respective variable current sources I1-I3controlled by the same gain control signals gc1-gc3. It should beapparent that each stage 402-406 can be implemented by using the PGAblock 102 of FIG. 2 and adding the variable current sources I1-I3. Thecircuit design principles discussed above relative to decreasing thecurrent in the amplifier may be required to be applied to all or some ofthe stages 402-404 of the multi-stage amplifier 400 in order to maintainits desired bandwidth. Further, the current level to each stage must beappropriately scaled in order to preserve the stability of themulti-stage amplifier.

In FIG. 5, there is shown a schematic circuit diagram of an exemplarycircuit design for implementing a portion of one stage 402 of themulti-stage amplifier 400 of FIG. 4. In other words, FIG. 5 is adetailed schematic of an operational amplifier 500 which is similar tothe amplifier 130 of FIG. 2, but in which the gain control signals alsocontrol the current levels, sizes of the input transistors, and sizes ofthe loading capacitors.

The operational amplifier 500 includes a pair of first and second inputtransistors M514, M515 having gates that are connected to the respectivenegative and positive input terminals inm1, inp1. The sources of theinput transistors are connected together and to the drain of a loadtransistor M513. The source of transistor M513 is connected to a powersupply VDD, and the gate thereof is connected to receive a bias voltagepbias. The positive output out+ is connected to the drain of the inputtransistor M514, and the negative output out− is connected to the drainof the input transistor M515.

In order to modify the current level, current control circuitry whichincludes series-connected current mirror transistors M4, M0 and M9 andthe respective switches SW1-SW3 are connected in parallel with the loadtransistor M513. The same gain control signals gc1-gc3 (FIG. 3) are usedto selectively close the switches SW1-SW3 for varying the current.Similarly, in order to modify the size of the first input transistor,transistor-size control circuitry including series-connected transistorsM7, M8 and Ml and their respective switches SW4-SW6 are connected inparallel therewith. Also, in order to modify the size of the secondinput transistor, transistor-size control circuitry including ofseries-connected transistors M2, M6 and M5 and their respective switchesSW7-SW9 are connected in parallel therewith. Again, the same gaincontrol signals gc1-gc3 are used to selectively close the switchesSW4-SW6 and SW7-SW9.

Further, a load capacitor C3 is connected between the positive andnegative outputs. In order to change the value of the load capacitor,capacitor-size control circuitry formed of series-connected capacitorsC0-C2 and their respective switches SW10-SW12 are connected in paralleltherewith. Likewise, the same gain control signals gel-gc3 are used toselectively close the switches SW10-SW12. The current control,transistor-size control, and capacitor-size control scheme can beexpanded by adding corresponding transistors or capacitors withassociated switches in parallel with the load transistor, inputtransistors, and load capacitor, respectively.

In the case of a switched capacitor delta-sigma modulator ADC, most ofthe noise is contributed by the switch noise given by kT/C and thethermal noise of the first integrator in the switched capacitordelta-sigma modulator. In order to reduce or save power in the ADC, thecurrent in the first integrator, which is basically an operationalamplifier similar to the amplifier 500 of FIG. 5, is reduced. As aresult, the thermal noise of the first integrator will increase for thesame reason as explained earlier for the operational amplifier 500. Thisreduction of current will also adversely affect the bandwidth of thefirst integrator. Therefore, the value of the integrating capacitor ofthe integrator has to be decreased so as to maintain the bandwidth. Thisdecrease will, in turn, necessitate a decrease in the value of thesampling capacitor of the integrator, thereby increasing the switchnoise.

In FIG. 6, there is shown a schematic circuit diagram of an exemplarycircuit design for implementing a front end portion 600 (samplingnetwork and first integrator) of a switched capacitor delta-sigmamodulator ADC. The front end portion 600 includes a first integrator602, a first bank 604 of sampling capacitors and switches, a second bank606 of sampling capacitors and switches, a third bank 608 of integratingcapacitors and switches, and a fourth bank 610 of integrating capacitorsand switches. The first integrator 602 is a differentialinput/differential output operational amplifier, which is constructedsimilar to the amplifier in FIG. 5. Thus, the first integrator isoperated in the same manner as the amplifier 500 wherein the same gaincontrol signals gc1-gc3 are also used to control or vary the amplifiercurrent (power), input transistor sizes, and load capacitor sizes.

The first bank 604 is formed of parallel-connected sampling capacitorsC12, C14, C15 and with series connected switches SW601-SW603interconnected to the input terminal 612 and the non-inverting input ofthe first integrator 602 and across a sampling capacitor C13. The secondbank 606 is formed of parallel-connected sampling capacitors C8, C9, C11and with series connected switches SW604-SW606 interconnected to theinput terminal 614 and the inverting input of the first integrator 602and across a sampling capacitor C10. The third bank 608 is formed ofparallel-connected integrating capacitors C4, C5, C7 and with seriesconnected switches SW607-SW609 interconnected to the non-inverting inputand the inverting output terminal 616 of the first integrator 602 andacross a sampling capacitor C6. The fourth bank 610 is formed ofparallel-connected integrating capacitors C0-C2 and with seriesconnected switches SW610-SW612 interconnected to the inverting input andthe non-inverting output terminal 618 of the first integrator 602 andacross a sampling capacitor C3.

In operation, in the first state, all of the switches φ1 are closed andall of the switches φ2 are opened so as to allow the input signals Vin+and Vin− applied to the input terminals 612 and 614 to charge up one ofthe sampling capacitors C12-C15 and one of the sampling capacitor C8-C11dependent upon the operation of the corresponding switches SW601-SW606.In the second state, all of the switches φ2 are closed and all of theswitches φ1 are opened so as to allow the voltages stored on theparticular sampling capacitor during the first state to be transferredto the non-inverting and inverting inputs of the integrator and to oneof the integrating capacitors C4-C7 and one of the integratingcapacitors C0-C3 dependent upon the operation of the switchesSW607-SW612. The same gain control signals gc1-gc3 are used again toselectively configure the switches SW601 through SW612.

Referring back again to the Tables I and II above, the total outputnoise and input-referred noise in Table II are not much different whencompared to the ones in the conventional data acquisition system ofTable I. Therefore, this comparison confirms that the noise performancein the system 200 of the present invention would be similar to thetraditional system 100. However, based upon the power managementdiscussed herein, the amplifier noise (second column in Table II) ismade higher at the lower gain settings so as to save power in theamplifier. In addition, the ADC noise (third column of Table II) is madehigher at the higher gain settings so as to save power in the ADC. Inthis example, the power consumption in the present system will be equalto the power consumption in the traditional system at the gain settingof 8. Nevertheless, it should be appreciated by those skilled in the artthat the particular gain setting can be optimized for a desiredapplication. By applying this power management concept in accordancewith the present invention, significant overall power savings can beachieved by dynamically adjusting power from the PGA to the ADC and fromthe ADC to the PGA as the gain settings of the amplifier are changed.

From the foregoing detailed description, it can thus be seen that thepresent invention provides a data acquisition system which includes aprogrammable gain amplifier, an analog-to-digital converter, a filter,and control circuitry. The control circuitry of the present invention isoperatively connected to the amplifier and to the converter and is alsoresponsive to gain control signals for dynamically adjusting powerbetween the amplifier and converter when the gain control signals arechanged.

While there has been illustrated and described what is at presentconsidered to be a preferred embodiment of the present invention, itwill be understood by those skilled in the art that various changes andmodifications may be made, and equivalents may be substituted forelements thereof without departing from the true scope of the invention.In addition, many modifications may be made to adapt a particularsituation or material to the teachings of the invention withoutdeparting from the central scope thereof. Therefore, it is intended thatthis invention not be limited to the particular embodiment disclosed asthe best mode contemplated for carrying out the invention, but that theinvention will include all embodiments falling within the scope of theappended claims.

1-20. (canceled)
 21. A data acquisition system, comprising: aprogrammable gain amplifier operatively connected to receive an analoginput signal on its input and to generate an amplified signal on itsoutput in accordance with gain control signals; an analog-to-digitalconverter operatively connected to receive the amplified signal fromsaid amplifier and to generate a digitized signal on its output; firstcurrent control circuitry coupled to said amplifier and being alsoresponsive to said gain control signals for controlling the currentlevel in said amplifier; and second current control circuitry coupled tosaid converter and being also responsive to said gain control signalsfor controlling the current level in said converter.
 22. A dataacquisition system as claimed in claim 21, wherein said first currentcontrol circuitry for controlling the current level in said amplifier isoperated in a manner so as to decrease the current level when said gaincontrol signals produce a relatively low gain setting in said amplifier,thereby reducing the overall power consumption of the system.
 23. A dataacquisition system as claimed in claim 21, wherein said second currentcontrol circuitry for controlling the current level in said converter isoperated in a manner so as to decrease the current level when said gaincontrol signals produce a relatively high gain setting in saidamplifier, thereby reducing the overall power consumption of the system.24. A data acquisition system as claimed in claim 21, wherein said firstcurrent control circuitry for controlling the current level in saidamplifier is operated in a manner so as to decrease the current leveland said second current control circuitry for controlling the currentlevel in said converter is operated in a manner so as to increase thecurrent level when said gain control signals produce a relatively lowgain setting in said amplifier, thereby dynamically adjusting power fromsaid amplifier to said converter.
 25. A data acquisition system asclaimed in claim 21, wherein said first current control circuitry forcontrolling the current level in said amplifier is operated in a mannerso as to increase the current level and said second current controlcircuitry for controlling the current level in said converter isoperated in a manner so as to decrease the current level when said gaincontrol signals produce a relatively high gain setting in saidamplifier, thereby dynamically adjusting power from said converter tosaid amplifier.
 26. A data acquisition system as claimed in claim 21,wherein said first current control circuitry includes a plurality offirst current mirror transistors and first switches, said first switchesbeing selectively configured to change the current level in saidamplifier.
 27. A data acquisition system as claimed in claim 26, whereinsaid second current control circuitry includes a plurality of secondcurrent mirror transistors and second switches, said second switchesbeing selectively configured to change the current level in saidconverter.
 28. A data acquisition system as claimed in claim 21, furthercomprising third control circuitry coupled to said amplifier and beingresponsive also to said gain control signals for changing the sizes ofinput transistors in said amplifier.
 29. A data acquisition system asclaimed in claim 28, further comprising fourth control circuitry coupledto said amplifier and being responsive also to said gain control signalsfor changing the sizes of load capacitors in said amplifier.
 30. A dataacquisition system as claimed in claim 21, wherein said amplifier isformed of a multi-stage amplifier in which each stage has currentcontrol circuitry responsive to said gain control signals forcontrolling the current level therein.
 31. A data acquisition system asclaimed in claim 21, wherein said analog-to-digital converter is anoversampling analog-to-digital converter.
 32. A data acquisition systemas claimed in claim 31, wherein said oversampling analog-to-digitalconverter is a delta-sigma analog-to-digital converter.
 33. A dataacquisition system as claimed in claim 21, wherein saidanalog-to-digital converter is a non-oversampling analog-to-digitalconverter.
 34. A data acquisition system, comprising: a programmablegain amplifier operatively connected for receiving an analog inputsignal and for generating an amplified output signal in accordance withgain control signals; an analog-to-digital converter operativelyconnected for receiving the amplified output signal from saidprogrammable gain amplifier and for generating a digitized outputsignal; and control circuitry operatively connected to said programmablegain amplifier and to said analog-to-digital converter and being alsoresponsive to said gain control signals for dynamically adjusting powerbetween said programmable gain amplifier and said analog-to-digitalconverter when said gain control signals are changed.
 35. A dataacquisition system as claimed in claim 34, wherein said controlcircuitry includes first current control circuitry for controlling thecurrent level in said programmable gain amplifier so as to decrease thesame when said gain control signals produce a relatively low gainsetting in said programmable gain amplifier, thereby reducing theoverall power consumption of the system.
 36. A data acquisition systemas claimed in claim 35, wherein said control circuitry further includessecond current control circuitry for controlling the current level insaid analog-to-digital converter so as to decrease the same when saidgain control signals produce a relatively high gain setting in saidprogrammable gain amplifier, thereby reducing the overall powerconsumption of the system.
 37. A data acquisition system as claimed inclaim 34, wherein said control circuitry includes first current controlcircuitry for controlling the current level in said programmable gainamplifier so as to decrease the same and second current control meansfor controlling the current level in said analog-to-digital converter soas to increase the same when said gain control signals produce arelatively low gain setting in said programmable gain amplifier, therebydynamically adjusting power from said amplifier means to saidanalog-to-digital converter.
 38. A data acquisition system as claimed inclaim 34, wherein said control circuitry includes first current controlcircuitry for controlling the current level in said programmable gainamplifier so as to increase the same and second current controlcircuitry for controlling the current level in said analog-to-digitalconverter so as to decrease the same when said gain control signalsproduce a relatively high gain setting in said programmable gainamplifier, thereby dynamically adjusting power from saidanalog-to-digital converter to said programmable gain amplifier.
 39. Adata acquisition system as claimed in claim 34, wherein saidanalog-to-digital converter is an oversampling analog-to-digitalconverter.
 40. A data acquisition system as claimed in claim 39, whereinsaid oversampling analog-to-digital converter is a delta-sigmaanalog-to-digital converter.
 41. A data acquisition system as claimed inclaim 34, wherein said analog-to-digital converter is a non-oversamplinganalog-to-digital converter.
 42. A method for reducing overall power ina data acquisition system, comprising: amplifying an analog input signalwith a programmable gain amplifier to generate an amplified signal inaccordance with gain control signals; converting the amplified signalwith an analog-to-digital converter to generate a digitized signal; anddynamically adjusting power between the programmable gain amplifier andthe analog-to-digital converter when the gain control signals arechanged.
 43. A method for reducing overall power in a data acquisitionsystem as claimed in claim 42, wherein adjusting power includescontrolling the current level in said programmable gain amplifier so asto decrease the same when the gain control signals produce a relativelylow gain setting in the programmable gain amplifier, thereby reducingthe overall power consumption of the system.
 44. A method for reducingoverall power in a data acquisition system as claimed in claim 42,wherein adjusting power includes controlling the current level in theanalog-to-digital converter so as to decrease the same when the gaincontrol signals produces a relatively high gain setting in theprogrammable gain amplifier, thereby reducing the overall powerconsumption of the system.
 45. A method for reducing overall power in adata acquisition system as claimed in claim 42, wherein adjusting powerincludes controlling the current level in the programmable gainamplifier so as to decrease the same and controlling the current levelin the analog-to-digital converter so as to increase the same when thegain control signals produce a relatively low gain setting in theprogrammable gain amplifier, thereby dynamically adjusting the powerfrom the programmable gain amplifier to the analog-to-digital converter.46. A method for reducing overall power in a data acquisition system asclaimed in claim 42, wherein adjusting power includes controlling thecurrent level in the programmable gain amplifier so as to increase thesame and controlling the current level in the analog-to-digitalconverter so as to decrease the same when said gain control signalsproduce a relatively high gain setting in the programmable gainamplifier, thereby dynamically adjusting the power from theanalog-to-digital converter to the programmable gain amplifier.
 47. Amethod for reducing overall power in a data acquisition system asclaimed in claim 42, wherein said analog-to-digital converter is anoversampling analog-to-digital converter.
 48. A method for reducingoverall power in a data acquisition system as claimed in claim 47,wherein said oversampling analog-to-digital converter is a delta-sigmaanalog-to-digital converter.
 49. A method for reducing overall power ina data acquisition system as claimed in claim 42, wherein saidanalog-to-digital converter is a non-oversampling analog-to-digitalconverter.